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preliminary rev. 0.4 2/08 copyright ? 2008 by silicon laboratories si5365 this information applies to a product under dev elopment. its characteristics and specifications are s ubject to change without n otice. si5365 p in -p rogrammable p recision c lock m ultiplier description the si5365 is a low jitter, pr ecision clock multiplier for high-speed communication systems, including sonet oc-48/oc-192, ethernet, and fibre channel, in which the application requires cl ock multiplication without jitter attenuation. the si5365 accepts four clock inputs ranging from 19.44 to 707 mhz and generates five frequency-multiplied clock outputs ranging from 19.44 to 1050 mhz. the input clock frequency and clock multiplication ratio are selectable from a table of popular sonet, ethernet, and fibre channel rates. the si5365 is based on silicon laboratories' 3rd- generation dspll ? technology, which provides any- rate frequency synthesis in a highly integrated pll solution that eliminates the need for external vcxo and loop filter components. the dspll loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. operating from a single 1.8 or 2.5 v supply, the si5365 is ideal for providing clock multiplication in high performance timing applications. applications ? sonet/sdh oc-48/stm-16 and stm-64/oc-192 line cards ? gbe/10gbe, 1/2/4/8/10gfc line cards ? itu g.709 line cards ? test and measurement features ? selectable output frequencies ranging from 19.44 to 1050 mhz ? low jitter clock outputs w/jitter generation as low as 0.6 ps rms (50 khz?80 mhz) ? integrated loop filter with selectable loop bandwidth (30 khz to 1.3 mhz) ? four clock inputs w/manual or automatically controlled switching ? five clock outputs with selectable signal format (lvpecl, lvds, cml, cmos) ? support for itu g.709 fec ratios (255/238, 255/237, 255/236) ? los alarm outputs ? digitally-controlled ou tput phase adjust ? pin-programmable settings ? on-chip voltage regulator for 1.8 5% or 2.5 v 10% operation ? small size: 14 x 14 mm 100-pin tqfp ? pb-free, rohs compliant p reliminary d ata s heet manual/auto switch ckout2 ckin1 ckout1 ckin2 control nc1 nc2 clock select ckin3 ckin4 ckout4 nc4 ckout5 nc5 vdd (1.8 or 2.5 v) gnd n32 n31 dspll ? n2 ckout3 nc3 n33 n34 los/fos alarms frequency select bandwidth select divider select
si5365 2 preliminary rev. 0.4 table 1. performance specifications (v dd = 1.8 5% or 2.5 v 10%, t a = ?40 to 85 oc) parameter symbol test co ndition min typ max unit temperature range t a ?40 25 85 oc supply voltage v dd 2.25 2.5 2.75 v 1.71 1.8 1.89 v supply current i dd f out = 622.08 mhz all ckouts enabled lvpecl format output ?394435ma only ckout1 enabled ? 253 284 ma f out = 19.44 mhz all ckouts enabled cmos format output ?278321ma only ckout1 enabled ? 229 261 ma tristate/sleep mode ? tbd tbd ma input clock frequency (ckin1, ckin2, ckin3, ckin4) ck f input frequency and clock multi- plication ratio pin-selectable from table of values using frqsel and frqtbl settings. consult silicon laboratorie s configuration software dspll sim or any-rate precision clock family reference manual at www.silabs.com/timing (click on documentation) for table selections. 19.44 ? 707.35 mhz output clock frequency (ckout1, ckout2, ckout3, ckout4, ckout5) ck of 19.44 ? 1049.76 mhz 3-level input pins input mid current i imm see note 2. ?2 ? 2 a input clocks (ckin1, ckin2, ckin3, ckin4) differential voltage swing ckn dpp 0.25 ? 1.9 v pp common mode voltage ckn vcm 1.8 v 5% 0.9 ? 1.4 v 2.5 v 10% 1.0 ? 1.7 v rise/fall time ckn trf 20?80% ? ? 11 ns duty cycle (minimum pulse width) ckn dc whichever is smaller 40 ? 60 % 2??ns output clocks (ckout1, ck out2, ckout3, ckout4, ckout5) common mode v ocm lvpecl 100 load line-to-line v dd ?1.42 ? v dd ?1.25 v differential output swing v od 1.1 ? 1.9 v single ended output swing v se 0.5 ? 0.93 v rise/fall time cko trf 20?80% ? 230 350 ps duty cycle certainty cko dc lvpecl differential 10 line-to-line measured at 50% point ?40 ? 40 ps notes: 1. for a more comprehensive listing of device specifications , please consult the silicon laboratories any-rate precision clock family reference manual. th is document can be downloaded from www.silabs.com/timing (click on documentation) . 2. this is the amount of leakage that the 3 level input can tolerate from an external driver. see the family reference manual. in most designs, an external resistor voltage divider is recommended.
si5365 preliminary rev. 0.4 3 pll performance jitter generation j gen f in = f out = 622.08 mhz, lvpecl output format 50 khz?80 mhz ? 0.6 tbd ps rms 12 khz?20 mhz ? 0.6 tbd ps rms jitter transfer j pk ?0.050.1db phase noise cko pn f in = f out = 622.08 mhz 100 hz offset ? tbd tbd dbc/hz 1 khz offset ? tbd tbd dbc/hz 10 khz offset ? tbd tbd dbc/hz 100 khz offset ? tbd tbd dbc/hz 1 mhz offset ? tbd tbd dbc/hz subharmonic noise sp subh phase noise @ 100 khz offset ? tbd tbd dbc spurious noise sp spur max spur @ n x f3 (n > 1, n x f3 < 100 mhz) ? tbd tbd dbc package thermal resistance junction to ambient ja still air ? 40 ? oc/w table 2. absolute maximum ratings parameter symbol value unit dc supply voltage v dd ?0.5 to 2.75 v lvcmos input voltage v dig ?0.3 to (v dd + 0.3) v operating junction temperature t jct ?55 to 150 oc storage temperature range t stg ?55 to 150 oc esd hbm tolerance (100 pf, 1.5 k ? ); all pins except ckin+/ckin? 2 kv esd mm tolerance; all pins except ckin+/ckin? 200 v esd hbm tolerance (100 pf, 1.5 k ? ); ckin+/ckin? 700 v esd mm tolerance; ckin+/ckin? 150 v latch-up tolerance jesd78 compliant note: permanent device damage may occur if the absolute maximu m ratings are exceeded. functional operation should be restricted to the conditions as specified in the operation se ctions of this data sheet. exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. table 1. performance specifications (continued) (v dd = 1.8 5% or 2.5 v 10%, t a = ?40 to 85 oc) parameter symbol test co ndition min typ max unit notes: 1. for a more comprehensive listing of device specifications , please consult the silicon laboratories any-rate precision clock family reference manual. th is document can be downloaded from www.silabs.com/timing (click on documentation) . 2. this is the amount of leakage that the 3 level input can tolerate from an external driver. see the family reference manual. in most designs, an external resistor voltage divider is recommended.
si5365 4 preliminary rev. 0.4 figure 1. typical phase noise plot jitter bandwidth rms jitter (fs) oc-48, 12 khz to 20 mhz 374 oc-192, 20 khz to 80 mhz 388 oc-192, 4 mhz to 80 mhz 181 oc-192, 50 khz to 80 mhz 377 broadband, 800 hz to 80 mhz 420 622 mhz in, 622 mhz out bw=877 khz -170 -150 -130 -110 -90 -70 -50 1000 10000 100000 1000000 10000000 100000000 offset frequency (hz) phase noise (dbc/hz)
si5365 preliminary rev. 0.4 5 figure 2. si5365 typical application circuit si5365 ckin1+ ckin1? cksel[1:0] 3 alrmout cnb rst ckout1+ ckout1? vdd gnd input clock sources 1 input clock select reset alarm output indicator ckin_n invalid indicator (n = 1 to 3) clock outputs 2. denotes tri-level input pins with states designated as l (ground), m (v dd /2), and h (v dd ). ckout5+ ckout5? autosel 2 manual/automatic clock selection (l) bwsel[1:0] 2 bandwidth select frqsel[3:0] 2 frequency select frqtbl 2 frequency table select sfout[1:0] 2 signal format select dbl2_by 2 dbl34 clock output 2 disable/ bypass mode control clock outputs 3 and 4 disable dbl5 2 ckout5 disable div34[1:0] 2 ckout_3 and ckout_4 divider control ckin4+ ckin4? 1. assumes differential lvpecl termination (3.3 v) on clock inputs. notes: 3. assumes manual input clock selection. ferrite bead system power supply c 10 c 1?9 0.1 f 1 f 0.1 f 100 0.1 f + ? 0.1 f 100 0.1 f + ? 130 130 82 82 v dd = 3.3 v 130 130 82 82 v dd = 3.3 v v dd 15 k 15 k v dd 15 k 15 k v dd 15 k 15 k v dd 15 k 15 k v dd 15 k 15 k v dd 15 k 15 k v dd 15 k 15 k v dd 15 k 15 k
si5365 6 preliminary rev. 0.4 1. functional description the si5365 is a low jitter, precision clock multiplier for high-speed communication systems, including sonet oc-48/oc-192, sdh stm-16/stm-64, ethernet, and fibre channel, in which the application requires clock multiplication without jitte r attenuation. the si5365 accepts four clock inputs ranging from 19.44 to 707 mhz and generates five frequency-multiplied clock outputs ranging from 19.44 to 1050 mhz. by default the four clock inputs are at the same frequency and the five clock outputs are at the same frequency. two of the output clocks can be divi ded down further to generate an integer sub-multiple frequency. the input clock frequency and clock multiplication ratio are selectable from a table of popular sonet, ethernet, and fibre channel rates. in addition to providing clock multiplication in sonet and datacom applications, the si5365 supports sonet-to-datacom frequency translations. silicon laboratories offers a pc-based software utility, dspll sim , that can be used to look up valid si5365 frequen cy translations. this utility can be downloaded from http://www.silabs.com/timing (click on documentation). the si5365 is based on s ilicon laboratories' 3rd- generation dspll ? technology, which provides any- rate frequency synthesis in a highly integrated pll solution that eliminates the need for external vcxo and loop filter components. the si5365 pll loop bandwidth is digitally programmable vi a the bwsel[1:0] pins and supports a range from 30 khz to 1.3 mhz. the dspll sim software utility can be used to calculate valid loop bandwidth settings for a given input clock frequency/clock mu ltiplication ratio. the si5365 monitors all input clocks for loss-of-signal and provides a los alarm when it detects a missing clock. in the case when the input clocks enter alarm conditions, the pll will freeze the dco output frequency near its last val ue to maintain operation with an internal state close to the last valid operating state. the si5365 has five differential clock outputs. the signal format of the clock outputs is programmable to support lvpecl, lvds, cml, or cmos loads. if not required, unused clock outputs can be powered down to minimize power consumption. for system-level debugging, a bypass mode is available which drives the output clock directly from th e input clock, bypassing the internal dspll. the device is powered by a single 1.8 or 2.5 v supply. 1.1. further documentation consult the silicon laborato ries any-rate precision clock family reference ma nual (frm) for detailed information about the si5365. additional design support is available from silicon laboratories through your distributor. silicon laboratories has developed a pc-based software utility called dspll sim to simplify device configuration, including frequency planning and loop bandwidth selection. the frm and this utility can be downloaded from http://www.silabs.com/timing ; click on documentation.
si5365 preliminary rev. 0.4 7 2. pin descriptions: si5365 table 3. si5365 pin descriptions pin # pin name i/o signal level description 1, 2, 17, 20, 23, 24, 25, 47, 48, 49, 52, 53, 72, 73, 74, 75, 90 nc no connect. these pins must be left unconnected for normal operation. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 31 30 29 28 27 26 32 64 61 62 63 57 58 59 60 50 51 52 53 54 55 56 49 autosel nc nc gnd c2b gnd c1b c3b alrmout gnd nc vdd ckin3+ ckin3? vdd ckin1+ ckin1? dbl2_by ckin2+ ckin2? vdd ckin4+ ckin4? nc dbl5 gnd frqsel3 div34_1 div34_0 frqsel1 frqsel0 gnd vdd bwsel1 bwsel0 c2a c1a cs1_c4a fos_ctl gnd ckout3+ nc ckout3? sfout0 ckout1+ ckout1? ckout5+ ckout5? vdd ckout2+ ckout2? sfout1 ckout4+ dsbl34 ckout4? 17 20 19 18 24 23 22 21 25 74 73 72 71 70 69 68 67 66 65 75 100 89 90 91 92 93 94 95 96 97 98 99 76 77 78 79 80 81 82 83 84 85 86 87 88 rst frqtbl nc vdd gnd cs0_c3a gnd gnd gnd nc nc nc gnd vdd gnd gnd gnd gnd gnd gnd gnd gnd vdd frqsel2 gnd nc vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd nc nc nc nc nc vdd nc nc si5365 gnd pad gnd
si5365 8 preliminary rev. 0.4 3rst ilvcmos external reset. active low input that performs external hardware reset of device. resets all internal logic to a known state and forces the device registers to their default value. clock outputs are tristat ed during reset. after rising edge of rst signal, the device will perform an internal self-calibration. this pin has a weak pullup. 4 frqtbl i 3-level frequency table select. this pin selects sonet/sdh, dataco m, or sonet/sdh to datacom fre- quency translation table. l = sonet/sdh. m=datacom. h = sonet/sdh to datacom. this pin has a weak pullup and weak pulldown and defaults to m. some designs may require an external resistor voltage divider when driven by an active device that will tri-state. 5, 6, 15, 27, 32, 42, 62, 63, 76, 79, 81, 84, 86, 89, 91, 94, 96, 99, 100 v dd v dd supply v dd . the device operates from a 1.8 or 2. 5 v supply. bypass capacitors should be associated with the following v dd pins: pins bypass cap 5, 6 0.1 f 15 0.1 f 27 0.1 f 62, 63 0.1 f 76, 79 1.0 f 81, 84 0.1 f 86, 89 0.1 f 91, 94 0.1 f 96, 99, 100 0.1 f 7, 8, 14, 16, 18, 19, 21, 26, 28, 31, 33, 36, 38, 41, 43, 46, 51, 54, 55, 56, 64, 65 gnd gnd supply ground. these pins must be connected to s ystem ground. minimize the ground path impedance for optimal performance. 9c1bolvcmos ckin1 invalid indicator. this pin is an active high alarm output associated with ckin1. once trig- gered, the alarm will remain high until ckin1 is validated. 0 = no alarm on ckin1. 1 = alarm on ckin1. 10 c2b o lvcmos ckin2 invalid indicator. this pin is an active high alarm output associated with ckin2. once trig- gered, the alarm will remain high until ckin2 is validated. 0 = no alarm on ckin2. 1 = alarm on ckin2. table 3. si5365 pin descriptions (continued) pin # pin name i/o signal level description
si5365 preliminary rev. 0.4 9 11 c3b o lvcmos ckin3 invalid indicator. this pin is an active high alarm output associated with ckin3. 0 = no alarm on ckin3. 1 = alarm on ckin3. 12 alrmout o lvcmos alarm output indicator. this pin is an active high alarm ou tput associated with ckin4 or the frame sync alignment alarm. 0 = alrmout not active. 1 = alrmout active. 13 57 cs0_c3a cs1_c4a i/o lvcmos input clock select/ckinn active clock indicator. input : if manual clock selection mode is chosen (autosel = 1), the cs[1:0] pins function as the manu al input clock selector control. these inputs are internally deglitched to prevent inadvertent clock switching during changes in the csn input state. if config- ured as input, these pins must not float. output : if automatic clock detection is chosen (autosel = m or h), these pins function as the ckinn active clock indicator output. 0 = ckinn is not the active input clock. 1 = ckinn is currently the active input clock to the pll. this pin has a weak pulldown. 22 autosel i 3-level manual/automatic clock selection. three level input that selects the meth od of input clock selection to be used. l = manual. m = automatic non-revertive. h = automatic revertive. this pin has a weak pullup and weak pulldown and defaults to m. some designs may require an external resistor voltage divider when driven by an active device that will tri-state. 29 30 ckin4+ ckin4? imulti clock input 4. differential clock input. this input can also be driven with a single-ended signal. 34 35 ckin2+ ckin2? imulti clock input 2. differential input clock. this input can also be driven with a single-ended signal. table 3. si5365 pin descriptions (continued) pin # pin name i/o signal level description cs[1:0] active input clock 00 ckin1 01 ckin2 10 ckin3 11 ckin4
si5365 10 preliminary rev. 0.4 37 dbl2_by i 3-level ckout2 disable/pll bypass mode control. controls enable of ckout2 divider/ output buffer path and pll bypass mode. l = ckout2 enabled. m = ckout2 disabled. h = bypass mode with ckout2 enabled. this pin has a weak pullup and weak pulldown and defaults to m. some designs may require an external resistor voltage divider when driven by an active device that will tri-state. 39 40 ckin3+ ckin3? imulti clock input 3. differential clock input. this input can also be driven with a single-ended signal. 44 45 ckin1+ ckin1? imulti clock input 1. differential clock input. this input can also be driven with a single-ended signal. 50 dbl5 i 3-level ckout5 disable. this pin performs the following functions: l = normal operation. output path is active and signal format is deter- mined by sfout inputs. m = cmos signal format. override s sfout signal format to allow ckout5 to operate in cmos format while the clock outputs operate in a differential output format. h = powerdown. entire ckout5 divider and output buffer path is pow- ered down. ckout5 output will be in tristate mode during powerdown. this pin has a weak pullup and weak pulldown and defaults to m. some designs may require an external resistor voltage divider when driven by an active device that will tri-state. 56 fos_ctl i 3-level frequency offset control. this pin enables or disables use of the ckin2 fos reference as an input to the clock selection state machine. l = fos disabled. m = stratum 3/3e fos threshold. h = sonet minimum clock fos threshold. this pin has both weak pullups and weak pulldowns and defaults to m. some designs may require an external resistor voltage divider when driven by an active device that will tri-state. 58 c1a o lvcmos ckin1 active clock indicator. this pin serves as the ckin 1 active clock indicator. 0 = ckin1 is not the active input clock. 1 = ckin1 is currently the active input clock to the pll. 59 c2a o lvcmos ckin2 active clock indicator. this pin serves as the ckin 2 active clock indicator. 0 = ckin2 is not the active input clock. 1 = ckin2 is currently the active input clock to the pll. table 3. si5365 pin descriptions (continued) pin # pin name i/o signal level description
si5365 preliminary rev. 0.4 11 60 61 bwsel0 bwsel1 i 3-level bandwidth select. these pins are three level inputs that select the dspll closed loop band- width according to the any-rate precision clock family reference man- ual. these pins have both weak pullups and weak pulldowns and default to m. some designs may require an external resistor voltage divider when driven by an active device that will tri-state. 66 67 div34_0 div34_1 i 3-level ckout3 and ckout4 divider control. these pins control the division of ckout3 and ckout4 relative to the ckout2 output frequency. detailed oper ations and timing characteristics for these pins may be found in the any-rate precision clock family ref- erence manual. these pins have both weak pullups and weak pulldowns and default to m. some designs may require an external resistor voltage divider when driven by an active device that will tri-state. 68 69 70 71 frqsel0 frqsel1 frqsel2 frqsel3 i 3-level multiplier select. these pins are three level inputs that select the input clock and clock mul- tiplication setting according to the an y-rate precision clock family ref- erence manual, depending on the frqtbl setting. these pins have both weak pullups and weak pulldowns and default to m. some designs may require an external resistor voltage divider when driven by an active device that will tri-state. 77 78 ckout3+ ckout3? omulti clock output 3. differential output clock with a frequency specified by frqsel and frqtbl settings. output is differential for lvpecl, lvds, and cml com- patible modes. for cmos format, both output pins drive identical single- ended clock outputs. 80 95 sfout1 sfout0 i 3-level signal format select. three level inputs that select the output signal format (common mode voltage and differential swing) for all of the clock outputs except ckout5 (see dbl5). these pins have both weak pullups and weak pulldowns and default to m. some designs may require an external resistor voltage divider when driven by an active device that will tri-state. table 3. si5365 pin descriptions (continued) pin # pin name i/o signal level description sfout[1:0] signal format hh reserved hm lvds hl cml mh lvpecl mm reserved ml lvds?low swing lh cmos lm disable ll reserved
si5365 12 preliminary rev. 0.4 82 83 ckout1? ckout1+ omulti clock output 1. differential output clock with a fr equency specified by frqsel and frqtbl. output signal format is selected by sfout pins. output is dif- ferential for lvpecl, lvds, and cml compatible modes. for cmos for- mat, both output pins drive identical single-ended clock outputs. 85 dbl34 i lvcmos output 3 and 4 disable. active high input. when active, ent ire ckout3 and ckout4 divider and output buffer path is powered do wn. ckout3 and ckout4 outputs will be in tristate mode during powerdown. this pin has a weak pullup. 87 88 ckout5? ckout5+ omulti clock output 5. fifth high-speed clock output with a frequency specified by frqsel and frqtbl. output signal format is selected by sfout pins. output is dif- ferential for lvpecl, lvds, and cml compatible modes. for cmos for- mat, both output pins drive identical single-ended clock outputs. 92 93 ckout2+ ckout2? omulti clock output 2. differential output clock with a fr equency specified by frqsel and frqtbl. output signal format is selected by sfout pins. output is dif- ferential for lvpecl, lvds, and cml compatible modes. for cmos for- mat, both output pins drive identical single-ended clock outputs. 97 98 ckout4? ckout4+ omulti clock output 4. differential output clock with a fr equency specified by frqsel and frqtbl settings. output signal format is selected by sfout pins. out- put is differential for lvpecl, lvds, and cml compatible modes. for cmos format, both output pins drive identical single-ended clock outputs. gnd pad gnd pad gnd supply ground pad . the ground pad must provide a low thermal and electrical impedance to a ground plane. table 3. si5365 pin descriptions (continued) pin # pin name i/o signal level description
si5365 preliminary rev. 0.4 13 3. ordering guide ordering part number package r ohs6, pb-free temperature range si5365-c-gq 100-pin 14 x 14 mm tqfp yes ?40 to 85 c
si5365 14 preliminary rev. 0.4 4. package outl ine: 100-pin tqfp figure 3 illustrates the package details for the si5365. table 4 lis ts the values for the di mensions shown in the illustration. figure 3. 100-pin thin quad flat package (tqfp) table 4. 100-pin package diagram dimensions dimension min nom max dimension min nom max a ? ? 1.20 e 16.00 bsc. a1 0.05 ? 0.15 e1 14.00 bsc. a2 0.95 1.00 1.05 e2 3.85 4.00 4.15 b 0.17 0.22 0.27 l 0.45 0.60 0.75 c 0.09 ? 0.20 aaa ? ? 0.20 d 16.00 bsc. bbb ? ? 0.20 d1 14.00 bsc. ccc ? ? 0.08 d2 3.85 4.00 4.15 ddd ? ? 0.08 e0.50 bsc. 0o 3.5o 7o notes: 1. all dimensions shown are in mil limeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this package outline conforms to jedec ms-026, variant aed-hd. 4. recommended card reflow profile is per the jede c/ipc j-std-020c specification for small body components.
si5365 preliminary rev. 0.4 15 5. recommended pcb layout figure 4. pcb land pattern diagram
si5365 16 preliminary rev. 0.4 table 5. pcb land pattern dimensions dimension min max e0.50 bsc. e 15.40 ref. d 15.40 ref. e2 3.90 4.10 d2 3.90 4.10 ge 13.90 ? gd 13.90 ? x ? 0.30 y1.50 ref. ze ? 16.90 zd ? 16.90 r1 0.15 ref r2 ? 1.00 notes (general): 1. all dimensions shown are in mil limeters (mm) unless otherwise noted. 2. dimensioning and tolerancing is per the ansi y14.5m-1994 specification. 3. this land pattern design is based on ipc-7351 guidelines. 4. all dimensions shown are at maximum material condition (mmc). least material condition (lmc) is calculated based on a fabrication allowance of 0.05 mm. notes (solder mask design): 1. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. notes (stencil design): 1. a stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. the stencil thickness shou ld be 0.125 mm (5 mils). 3. the ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads. 4. a 4 x 4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the center ground pad. notes (card assembly): 1. a no-clean, type-3 solder paste is recommended. 2. the recommended card reflow profile is per the jedec/ipc j-std-020c specification for small body components.
si5365 preliminary rev. 0.4 17 d ocument c hange l ist revision 0.32 to revision 0.33 ? condensed format. revision 0.33 to revision 0.34 ? removed references to latency control, inc, and dec pins. ? updated table 1, ?performance specifications,? on page 2. ? changed lvttl to lvcmos in table 2, ?absolute maximum ratings,? on page 3. ? added figure 1, ?typical phase noise plot,? on page 4. ? updated figure 2, ?si5365 typical application circuit?. ? updated ?2. pin descriptions: si5365?. ? updated "3. ordering guide" on page 13. ? added ?5. recommended pcb layout?. revision 0.34 to revision 0.4 ? changed 1.8 v operating range to 5%. ? updated table 1 on page 2. ? updated table 2 on page 3. ? added page 4. ? updated "1. functional description" on page 6. ? clarified "2. pin descriptions: si5365" on page 7 including the addition of fos_ctl (pin 56).
si5365 18 preliminary rev. 0.4 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 email: clockinfo@silabs.com internet: www.silabs.com silicon laboratories, silicon labs, and dspll are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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